/* sim-safe.c - sample functional simulator implementation */

/* SimpleScalar(TM) Tool Suite
 * Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
 * All Rights Reserved. 
 * 
 * THIS IS A LEGAL DOCUMENT, BY USING SIMPLESCALAR,
 * YOU ARE AGREEING TO THESE TERMS AND CONDITIONS.
 * 
 * No portion of this work may be used by any commercial entity, or for any
 * commercial purpose, without the prior, written permission of SimpleScalar,
 * LLC (info@simplescalar.com). Nonprofit and noncommercial use is permitted
 * as described below.
 * 
 * 1. SimpleScalar is provided AS IS, with no warranty of any kind, express
 * or implied. The user of the program accepts full responsibility for the
 * application of the program and the use of any results.
 * 
 * 2. Nonprofit and noncommercial use is encouraged. SimpleScalar may be
 * downloaded, compiled, executed, copied, and modified solely for nonprofit,
 * educational, noncommercial research, and noncommercial scholarship
 * purposes provided that this notice in its entirety accompanies all copies.
 * Copies of the modified software can be delivered to persons who use it
 * solely for nonprofit, educational, noncommercial research, and
 * noncommercial scholarship purposes provided that this notice in its
 * entirety accompanies all copies.
 * 
 * 3. ALL COMMERCIAL USE, AND ALL USE BY FOR PROFIT ENTITIES, IS EXPRESSLY
 * PROHIBITED WITHOUT A LICENSE FROM SIMPLESCALAR, LLC (info@simplescalar.com).
 * 
 * 4. No nonprofit user may place any restrictions on the use of this software,
 * including as modified by the user, by any other authorized user.
 * 
 * 5. Noncommercial and nonprofit users may distribute copies of SimpleScalar
 * in compiled or executable form as set forth in Section 2, provided that
 * either: (A) it is accompanied by the corresponding machine-readable source
 * code, or (B) it is accompanied by a written offer, with no time limit, to
 * give anyone a machine-readable copy of the corresponding source code in
 * return for reimbursement of the cost of distribution. This written offer
 * must permit verbatim duplication by anyone, or (C) it is distributed by
 * someone who received only the executable form, and is accompanied by a
 * copy of the written offer of source code.
 * 
 * 6. SimpleScalar was developed by Todd M. Austin, Ph.D. The tool suite is
 * currently maintained by SimpleScalar LLC (info@simplescalar.com). US Mail:
 * 2395 Timbercrest Court, Ann Arbor, MI 48105.
 * 
 * Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
 */


#include <stdio.h>
#include <stdlib.h>
#include <math.h>
/* ECE552 Assignment 2 - BEGIN CODE */
//need this library for the random predictor
#include <time.h>
/* ECE552 Assignment 2 - END CODE */
#include "host.h"
#include "misc.h"
#include "machine.h"
#include "regs.h"
#include "memory.h"
#include "loader.h"
#include "syscall.h"
#include "dlite.h"
#include "options.h"
#include "stats.h"
#include "sim.h"

/*
 * This file implements a functional simulator.  This functional simulator is
 * the simplest, most user-friendly simulator in the simplescalar tool set.
 * Unlike sim-fast, this functional simulator checks for all instruction
 * errors, and the implementation is crafted for clarity rather than speed.
 */


/* ECE552 Assignment 2 - STATS COUNTERS - BEGIN */ 

//total number of conditional branches
static counter_t sim_num_br = 0;
//number of mispredicted branches of the static predict-taken predictor
static counter_t sim_num_mispred_static = 0;
//number of mispredicted branches of the random predictor
static counter_t sim_num_mispred_random = 0;
//number of mispredicted branches of the 2-bit saturating counter predictor
static counter_t sim_num_mispred_2bitsat = 0;
//number of mispredicted branches of two level predictor
static counter_t sim_num_mispred_2level = 0;
//number of mispredicted branches of the open-ended predictor
static counter_t sim_num_mispred_openend = 0;

/* ECE552 Assignment 2 - STATS COUNTERS - END */ 

/* simulated registers */
static struct regs_t regs;

/* simulated memory */
static struct mem_t *mem = NULL;

/* track number of refs */
static counter_t sim_num_refs = 0;

/* maximum number of inst's to execute */
static unsigned int max_insts;

/* register simulator-specific options */
void
sim_reg_options(struct opt_odb_t *odb)
{
  opt_reg_header(odb, 
"sim-safe: This simulator implements a functional simulator.  This\n"
"functional simulator is the simplest, most user-friendly simulator in the\n"
"simplescalar tool set.  Unlike sim-fast, this functional simulator checks\n"
"for all instruction errors, and the implementation is crafted for clarity\n"
"rather than speed.\n"
		 );

  /* instruction limit */
  opt_reg_uint(odb, "-max:inst", "maximum number of inst's to execute",
	       &max_insts, /* default */0,
	       /* print */TRUE, /* format */NULL);

}

/* check simulator-specific option values */
void
sim_check_options(struct opt_odb_t *odb, int argc, char **argv)
{
  /* nada */
}

/* register simulator-specific statistics */
void sim_reg_stats(struct stat_sdb_t *sdb) {
    stat_reg_counter(sdb, "sim_num_insn",
            "total number of instructions executed",
            &sim_num_insn, sim_num_insn, NULL);
    stat_reg_counter(sdb, "sim_num_refs",
            "total number of loads and stores executed",
            &sim_num_refs, 0, NULL);
    stat_reg_int(sdb, "sim_elapsed_time",
            "total simulation time in seconds",
            &sim_elapsed_time, 0, NULL);
    stat_reg_formula(sdb, "sim_inst_rate",
            "simulation speed (in insts/sec)",
            "sim_num_insn / sim_elapsed_time", NULL);

    ld_reg_stats(sdb);
    mem_reg_stats(mem, sdb);

    stat_reg_counter(sdb, "sim_num_br",
            "total number of conditional branches",
            &sim_num_br, sim_num_br, NULL);

    stat_reg_formula(sdb, "sim_ratio_cond_br_insn",
            "Fraction of instructions that are conditional branches.",
            "sim_num_br / sim_num_insn", NULL);	

    stat_reg_counter(sdb, "sim_num_mispred_static",
            "Static preditor: number of mispredicted branches",
            &sim_num_mispred_static, sim_num_mispred_static, NULL);

    stat_reg_formula(sdb, "sim_br_static_ratio",
            "Static predictor: branch misprediction rate",
            "sim_num_mispred_static / sim_num_br", NULL);	

    stat_reg_counter(sdb, "sim_num_mispred_random",
            "Random preditor: number of mispredicted branches",
            &sim_num_mispred_random, sim_num_mispred_random, NULL);

    stat_reg_formula(sdb, "sim_br_random_ratio",
            "Random predictor: branch misprediction rate",
            "sim_num_mispred_random / sim_num_br", NULL);	

    stat_reg_counter(sdb, "sim_num_mispred_2bitsat",
            "2-bit sat. counter preditor: number of mispred. branches",
            &sim_num_mispred_2bitsat, sim_num_mispred_2bitsat, NULL);

    stat_reg_formula(sdb, "sim_br_2bitsat_ratio",
            "2-bit sat. counter predictor: branch misprediction rate",
            "sim_num_mispred_2bitsat / sim_num_br", NULL);

    stat_reg_counter(sdb, "sim_num_mispred_2level",
            "Two level preditor: number of mispredicted branches",
            &sim_num_mispred_2level, sim_num_mispred_2level, NULL);

    stat_reg_formula(sdb, "sim_br_2level_ratio",
            "Two level predictor: branch misprediction rate",
            "sim_num_mispred_2level / sim_num_br", NULL);	

    stat_reg_counter(sdb, "sim_num_mispred_openend",
            "Open-ended preditor: number of mispredicted branches",
            &sim_num_mispred_openend, sim_num_mispred_openend, NULL);

    stat_reg_formula(sdb, "sim_br_openend_ratio",
            "Open-ended predictor: branch misprediction rate",
            "sim_num_mispred_openend / sim_num_br", NULL);	
}

/* initialize the simulator */
void
sim_init(void)
{
  sim_num_refs = 0;

  /* allocate and initialize register file */
  regs_init(&regs);

  /* allocate and initialize memory space */
  mem = mem_create("mem");
  mem_init(mem);
}

/* load program into simulated state */
void
sim_load_prog(char *fname,		/* program to load */
	      int argc, char **argv,	/* program arguments */
	      char **envp)		/* program environment */
{
  /* load program text and data, set up environment, memory, and regs */
  ld_load_prog(fname, argc, argv, envp, &regs, mem, TRUE);

  /* initialize the DLite debugger */
  dlite_init(md_reg_obj, dlite_mem_obj, dlite_mstate_obj);
}

/* print simulator-specific configuration information */
void
sim_aux_config(FILE *stream)		/* output stream */
{
  /* nothing currently */
}

/* dump simulator-specific auxiliary simulator statistics */
void
sim_aux_stats(FILE *stream)		/* output stream */
{
  /* nada */
}

/* un-initialize simulator-specific state */
void
sim_uninit(void)
{
  /* nada */
}


/*
 * configure the execution engine
 */

/*
 * precise architected register accessors
 */

/* next program counter */
#define SET_NPC(EXPR)		(regs.regs_NPC = (EXPR))

/* current program counter */
#define CPC			(regs.regs_PC)

/* general purpose registers */
#define GPR(N)			(regs.regs_R[N])
#define SET_GPR(N,EXPR)		(regs.regs_R[N] = (EXPR))

#if defined(TARGET_PISA)

/* floating point registers, L->word, F->single-prec, D->double-prec */
#define FPR_L(N)		(regs.regs_F.l[(N)])
#define SET_FPR_L(N,EXPR)	(regs.regs_F.l[(N)] = (EXPR))
#define FPR_F(N)		(regs.regs_F.f[(N)])
#define SET_FPR_F(N,EXPR)	(regs.regs_F.f[(N)] = (EXPR))
#define FPR_D(N)		(regs.regs_F.d[(N) >> 1])
#define SET_FPR_D(N,EXPR)	(regs.regs_F.d[(N) >> 1] = (EXPR))

/* miscellaneous register accessors */
#define SET_HI(EXPR)		(regs.regs_C.hi = (EXPR))
#define HI			(regs.regs_C.hi)
#define SET_LO(EXPR)		(regs.regs_C.lo = (EXPR))
#define LO			(regs.regs_C.lo)
#define FCC			(regs.regs_C.fcc)
#define SET_FCC(EXPR)		(regs.regs_C.fcc = (EXPR))

#elif defined(TARGET_ALPHA)

/* floating point registers, L->word, F->single-prec, D->double-prec */
#define FPR_Q(N)		(regs.regs_F.q[N])
#define SET_FPR_Q(N,EXPR)	(regs.regs_F.q[N] = (EXPR))
#define FPR(N)			(regs.regs_F.d[(N)])
#define SET_FPR(N,EXPR)		(regs.regs_F.d[(N)] = (EXPR))

/* miscellaneous register accessors */
#define FPCR			(regs.regs_C.fpcr)
#define SET_FPCR(EXPR)		(regs.regs_C.fpcr = (EXPR))
#define UNIQ			(regs.regs_C.uniq)
#define SET_UNIQ(EXPR)		(regs.regs_C.uniq = (EXPR))

#else
#error No ISA target defined...
#endif

/* precise architected memory state accessor macros */
#define READ_BYTE(SRC, FAULT)						\
  ((FAULT) = md_fault_none, addr = (SRC), MEM_READ_BYTE(mem, addr))
#define READ_HALF(SRC, FAULT)						\
  ((FAULT) = md_fault_none, addr = (SRC), MEM_READ_HALF(mem, addr))
#define READ_WORD(SRC, FAULT)						\
  ((FAULT) = md_fault_none, addr = (SRC), MEM_READ_WORD(mem, addr))
#ifdef HOST_HAS_QWORD
#define READ_QWORD(SRC, FAULT)						\
  ((FAULT) = md_fault_none, addr = (SRC), MEM_READ_QWORD(mem, addr))
#endif /* HOST_HAS_QWORD */

#define WRITE_BYTE(SRC, DST, FAULT)					\
  ((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_BYTE(mem, addr, (SRC)))
#define WRITE_HALF(SRC, DST, FAULT)					\
  ((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_HALF(mem, addr, (SRC)))
#define WRITE_WORD(SRC, DST, FAULT)					\
  ((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_WORD(mem, addr, (SRC)))
#ifdef HOST_HAS_QWORD
#define WRITE_QWORD(SRC, DST, FAULT)					\
  ((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_QWORD(mem, addr, (SRC)))
#endif /* HOST_HAS_QWORD */

/* system call handler macro */
#define SYSCALL(INST)	sys_syscall(&regs, mem_access, mem, INST, TRUE)

/* ECE552 Assignment 2 - BEGIN CODE */

//defining some names here to make code more readable
enum PREDICTOR_STATE { STRONGLY_TAKEN, WEAKLY_TAKEN, WEAKLY_NOT_TAKEN, STRONGLY_NOT_TAKEN };

enum BRANCH_STATUS { NOT_TAKEN, TAKEN };

/* Defining a struct to act as a basic two bit saturating counter */
typedef struct {
    int state;
} TwoBitSatCounter;

/********************************************************
 * isConditionalBranch()
 * Checks the opcode passed in to see if it is a conditional branch
 ********************************************************/
int isConditionalBranch(unsigned int op) {
    return ((MD_OP_FLAGS(op) & (F_COND)) == (F_COND));
}

/********************************************************
 * checkBranchStatus()
 * Checks the regs struct to see if the current branch was taken or not
 ********************************************************/
int checkBranchStatus() {
    return (regs.regs_NPC != regs.regs_PC + sizeof(md_inst_t)) ? TAKEN : NOT_TAKEN;
}

/********************************************************
 * predictionOfStatic()
 * Always return TAKEN, as it is a static predictor
 ********************************************************/
int predictionOfStatic() {
    return TAKEN;
}

/********************************************************
 * predictionOfRandom()
 * Returns TAKEN randomly with probability of 0.5
 ********************************************************/
int predictionOfRandom() {
    return ((rand() % 2) == 1) ? TAKEN : NOT_TAKEN;
}

/********************************************************
 * predictAndUpdateTwoBitSatCounter()
 * Returns the prediction of the two bit saturating counter
 * and also updates its internal state
 ********************************************************/
int predictAndUpdateTwoBitSatCounter(TwoBitSatCounter * counter, int branchStatus) {
    int prediction;

    switch (counter->state) {
        case STRONGLY_TAKEN:
            prediction = TAKEN;
            counter->state = (branchStatus == prediction) ?
                STRONGLY_TAKEN : WEAKLY_TAKEN;
            break;
        case WEAKLY_TAKEN:
            prediction = TAKEN;
            counter->state = (branchStatus == prediction) ?
                STRONGLY_TAKEN : STRONGLY_NOT_TAKEN;
            break;
        case STRONGLY_NOT_TAKEN:
            prediction = NOT_TAKEN;
            counter->state = (branchStatus == prediction) ?
                STRONGLY_NOT_TAKEN : WEAKLY_NOT_TAKEN;
            break;
        case WEAKLY_NOT_TAKEN:
            prediction = NOT_TAKEN;
            counter->state = (branchStatus == prediction) ?
                STRONGLY_NOT_TAKEN : STRONGLY_TAKEN;
            break;
    }
    return prediction;
}

// defining some constants for the 2 bit sat pred
#define SIZE_OF_2BIT_SAT_COUNTER_PHT 4096 // 4096 2 bit counters, totalling 8192 bits in table
#define PC_MASK_FOR_2BIT_SAT_COUNTER_PHT 0x00007FF8 // 12 bits from bit 3 to bit 14

/********************************************************
 * predictionOfTwoBitSatCounter()
 * Returns the prediction of the two bit saturating counter
 ********************************************************/
int predictionOfTwoBitSatCounter(TwoBitSatCounter twoBitSatCounterPHT[SIZE_OF_2BIT_SAT_COUNTER_PHT], int branchStatus) {
    int index = (regs.regs_PC & PC_MASK_FOR_2BIT_SAT_COUNTER_PHT) >> 3;
    return predictAndUpdateTwoBitSatCounter(&(twoBitSatCounterPHT[index]), branchStatus);
}

// defining some constants for the 2 level pred
#define SIZE_OF_2LEVEL_PREDICTOR_PHT 512
#define NUM_PHT_IN_2LEVEL_PREDICTOR 8
#define GHR_MASK_FOR_2LEVEL_PREDICTOR 0x000001FF // 9 bits from 0 to 8
#define PC_MASK_FOR_2LEVEL_PREDICTOR 0x00000038 // 3 bits from bit 3 to bit 5

/********************************************************
 * predictionOfTwoLevelPredictor()
 * Returns the prediction of the 2 level predictor
 ********************************************************/
int predictionOfTwoLevelPredictor(TwoBitSatCounter twoLevelPredictorPHTS[NUM_PHT_IN_2LEVEL_PREDICTOR][SIZE_OF_2LEVEL_PREDICTOR_PHT], int globalHistoryRegister, int branchStatus) {
    int pht = (regs.regs_PC & PC_MASK_FOR_2LEVEL_PREDICTOR) >> 3;
    int index = globalHistoryRegister & GHR_MASK_FOR_2LEVEL_PREDICTOR;
    return predictAndUpdateTwoBitSatCounter(&(twoLevelPredictorPHTS[pht][index]), branchStatus);
}

// defining some constants for the open ended pred
#define SIZE_OF_OE_BHT 2048
#define SIZE_OF_OE_LOCAL_PHT 4096 //8192
#define SIZE_OF_OE_GLOBAL_PHT 32768
#define SIZE_OF_OE_TOUR_PRED 16384
#define GHR_GLOBAL_MASK_FOR_OE_PREDICTOR 0x00007FFF // 15 bits from 0 to 14
#define GHR_TOURNAMENT_MASK_FOR_OE_PREDICTOR 0x00003FFF // 14 bits from 0 to 13
#define BHT_MASK_FOR_OE_PREDICTOR 0x00000FFF // 12 bits from 0 to 11
#define PC_MASK_FOR_OE_PREDICTOR 0x00003FF8  // 11 bits from 3 to 13

/* Defining a struct to act as a basic 3 bit bit saturating counter */
typedef struct {
    int state;
} ThreeBitSatCounter;

enum THREE_BIT_SAT_COUNTER_STATE { NNN, NNT, NTN, NTT, TNN, TNT, TTN, TTT };

/********************************************************
 * predictAndUpdateThreeBitSatCounter()
 * Returns the prediction of the three bit saturating counter
 * and also updates its internal state
 ********************************************************/
int predictAndUpdateThreeBitSatCounter(ThreeBitSatCounter * counter, int branchStatus) {
    int prediction;

    int state = counter->state;

    if ((state == NNN) || (state == NNT) || (state == NTN) || (state == TNN))
        prediction = NOT_TAKEN;
    else
        prediction = TAKEN;

    counter->state = (((counter->state) << 1) | branchStatus) & 0x00000007;
    return prediction;
}

/* defining a struct for the tournament pred counter */
typedef struct {
    int state;
} TournamentCounter;

enum TOURNAMENT_STATE { STRONG_P1, WEAK_P1, WEAK_P2, STRONG_P2 };
enum TOURNAMENT_PRED { P1, P2 };

typedef struct {
    int BHT [SIZE_OF_OE_BHT];
    TwoBitSatCounter localPHT [SIZE_OF_OE_LOCAL_PHT];
    TwoBitSatCounter globalPHT [SIZE_OF_OE_GLOBAL_PHT];
    TournamentCounter tournamentPred [SIZE_OF_OE_TOUR_PRED];
} TournamentPredictor;

/********************************************************
 * predictAndUpdateTournamentCounter()
 * Returns the prediction of the tournament counter
 * and also updates its internal state
 ********************************************************/
int predictAndUpdateTournamentCounter( TournamentCounter * counter, int P1Correct, int P2Correct) {
    int prediction;

    switch (counter->state) {
        case STRONG_P1:
        case WEAK_P1:
            prediction = P1;
            break;
        case STRONG_P2:
        case WEAK_P2:
            prediction = P2;
            break;
    }

    switch (counter->state) {
        case STRONG_P1:
            if (P1Correct == 0 && P2Correct == 1)
                counter->state = WEAK_P1;
            break;
        case WEAK_P1:
            if (P1Correct == 0 && P2Correct == 1)
                counter->state = WEAK_P2;
            else if (P1Correct == 1 && P2Correct == 0)
                counter->state = STRONG_P1;
            break;
        case STRONG_P2:
            if (P1Correct == 1 && P2Correct == 0)
                counter->state = WEAK_P2;
            break;
        case WEAK_P2:
            if (P1Correct == 0 && P2Correct == 1)
                counter->state = STRONG_P2;
            else if (P1Correct == 1 && P2Correct == 0)
                counter->state = WEAK_P1;
            break;
    }
    return prediction;
}

/********************************************************
 * predictionOfOEPredictor()
 * Returns the prediction of the open ended predictor
 ********************************************************/
int predictionOfOEPredictor(TournamentPredictor * openEndedPredictor, int globalHistoryRegister, int branchStatus) {
    // first get the globalPHT prediction
    int globalPHTIndex = globalHistoryRegister & GHR_GLOBAL_MASK_FOR_OE_PREDICTOR;
    int globalPHTPred = predictAndUpdateTwoBitSatCounter(
            &((openEndedPredictor->globalPHT)[globalPHTIndex]), branchStatus);

    // then get the localPHT prediction
    int BHTIndex = (regs.regs_PC & PC_MASK_FOR_OE_PREDICTOR) >> 3;
    int BHTEntry = (openEndedPredictor->BHT)[BHTIndex];
    int localPHTIndex = BHTEntry & BHT_MASK_FOR_OE_PREDICTOR;
    int localPHTPred = predictAndUpdateTwoBitSatCounter(
            &((openEndedPredictor->localPHT)[localPHTIndex]), branchStatus);

    int tournamentIndex = globalHistoryRegister & GHR_TOURNAMENT_MASK_FOR_OE_PREDICTOR;
    int tournamentPred = predictAndUpdateTournamentCounter(
            &((openEndedPredictor->tournamentPred)[tournamentIndex]),
            localPHTPred == branchStatus,
            globalPHTPred == branchStatus);

    // update BHT
    (openEndedPredictor->BHT)[BHTIndex] = 
        (((openEndedPredictor->BHT)[BHTIndex]) << 1) | branchStatus;

    return tournamentPred == P1 ? localPHTPred : globalPHTPred;
}
/* ECE552 Assignment 2 - END CODE */
 
/* start simulation, program loaded, processor precise state initialized */
void sim_main(void) {
    md_inst_t inst;
    register md_addr_t addr;
    enum md_opcode op;
    register int is_write;
    enum md_fault_type fault;

    fprintf(stderr, "sim: ** starting functional simulation **\n");

    /* ECE552 Assignment 2 - BEGIN CODE */
    // initiallising the branch predictors

    //seeding the random number generator for the random predictor
    srand(time(NULL));

    //to hold the result of the branch insn
    int branchStatus;

    // defining the data structures for the global history register
    int globalHistoryRegister = NOT_TAKEN;

    // the PHT for the 2 bit sat counter
    TwoBitSatCounter twoBitSatCounterPHT[SIZE_OF_2BIT_SAT_COUNTER_PHT];

    // initiallizing the 2-bit sat counter predictor
    int i,j;
    for (i=0; i<SIZE_OF_2BIT_SAT_COUNTER_PHT; i++)
        twoBitSatCounterPHT[i].state = WEAKLY_NOT_TAKEN;

    // and the branch table phts
    TwoBitSatCounter twoLevelPredictorPHTS[NUM_PHT_IN_2LEVEL_PREDICTOR][SIZE_OF_2LEVEL_PREDICTOR_PHT];

    // initiallizing the 2 level predictor
    for (j=0; j<NUM_PHT_IN_2LEVEL_PREDICTOR; j++)
        for (i=0; i<SIZE_OF_2LEVEL_PREDICTOR_PHT; i++)
            twoLevelPredictorPHTS[j][i].state = WEAKLY_NOT_TAKEN;

    // declaring the open ended pred
    TournamentPredictor openEndedPredictor;

    // initiallizing the open ended predictor states
    for (i=0; i<SIZE_OF_OE_BHT; i++)
        openEndedPredictor.BHT[i] = NOT_TAKEN;

    for (i=0; i<SIZE_OF_OE_LOCAL_PHT; i++)
        openEndedPredictor.localPHT[i].state = WEAKLY_NOT_TAKEN;

    for (i=0; i<SIZE_OF_OE_GLOBAL_PHT; i++)
        openEndedPredictor.globalPHT[i].state = WEAKLY_NOT_TAKEN;

    for (i=0; i<SIZE_OF_OE_TOUR_PRED; i++)
        openEndedPredictor.tournamentPred[i].state = WEAK_P1;

    /* ECE552 Assignment 2 - END CODE */

    /* set up initial default next PC */
    regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);

    /* check for DLite debugger entry condition */
    if (dlite_check_break(regs.regs_PC, /* !access */0, /* addr */0, 0, 0))
        dlite_main(regs.regs_PC - sizeof(md_inst_t),
                regs.regs_PC, sim_num_insn, &regs, mem);

    while (TRUE)
    {
        /* maintain $r0 semantics */
        regs.regs_R[MD_REG_ZERO] = 0;
#ifdef TARGET_ALPHA
        regs.regs_F.d[MD_REG_ZERO] = 0.0;
#endif /* TARGET_ALPHA */

        /* get the next instruction to execute */
        MD_FETCH_INST(inst, mem, regs.regs_PC);

        /* keep an instruction count */
        sim_num_insn++;

        /* set default reference address and access mode */
        addr = 0; is_write = FALSE;

        /* set default fault - none */
        fault = md_fault_none;

        /* decode the instruction */
        MD_SET_OPCODE(op, inst);

        /* execute the instruction */
        switch (op)
        {
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3)\
            case OP:\
                    SYMCAT(OP,_IMPL);\
            break;
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT)\
            case OP:\
                    panic("attempted to execute a linking opcode");
#define CONNECT(OP)
#define DECLARE_FAULT(FAULT)\
            { fault = (FAULT); break; }
#include "machine.def"
            default:
                panic("attempted to execute a bogus opcode");
        }

        if (fault != md_fault_none)
            fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);

        if (verbose)
        {
            myfprintf(stderr, "%10n [xor: 0x%08x] @ 0x%08p: ",
                    sim_num_insn, md_xor_regs(&regs), regs.regs_PC);
            md_print_insn(inst, regs.regs_PC, stderr);
            if (MD_OP_FLAGS(op) & F_MEM)
                myfprintf(stderr, "  mem: 0x%08p", addr);
            fprintf(stderr, "\n");
            /* fflush(stderr); */
        }

        if (MD_OP_FLAGS(op) & F_MEM)
        {
            sim_num_refs++;
            if (MD_OP_FLAGS(op) & F_STORE)
                is_write = TRUE;
        }

        /* ECE552 Assignment 2 - BEGIN CODE */
        // code for checking the branch predictors

        if (isConditionalBranch(op)) {
            //incrementing the counter
            sim_num_br++;

            branchStatus = checkBranchStatus();

            // the static taken predictor predictor
            if (predictionOfStatic() != branchStatus)
                sim_num_mispred_static++;

            // the random predictor
            if (predictionOfRandom() != branchStatus)
                sim_num_mispred_random++;

            // the two bit saturating counter predictor
            if (predictionOfTwoBitSatCounter(twoBitSatCounterPHT, branchStatus) != branchStatus)
                sim_num_mispred_2bitsat++;

            // the two level predictor
            if (predictionOfTwoLevelPredictor(twoLevelPredictorPHTS, globalHistoryRegister, branchStatus) != branchStatus)
                sim_num_mispred_2level++;

            // the open ended predictor
            if (predictionOfOEPredictor(&openEndedPredictor, globalHistoryRegister, branchStatus) != branchStatus)
                sim_num_mispred_openend++;

            // after the predictions are done, update the GHR
            globalHistoryRegister = (globalHistoryRegister << 1) | branchStatus;
        }
                
        /* ECE552 Assignment 2 - END CODE */

        /* check for DLite debugger entry condition */
        if (dlite_check_break(regs.regs_NPC,
                    is_write ? ACCESS_WRITE : ACCESS_READ,
                    addr, sim_num_insn, sim_num_insn))
            dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, &regs, mem);

        /* go to the next instruction */
        regs.regs_PC = regs.regs_NPC;
        regs.regs_NPC += sizeof(md_inst_t);

        /* finish early? */
        if (max_insts && sim_num_insn >= max_insts)
            return;
    }
}
